A complementary metal-oxide-semiconductor (CMOS) inverter is a basic semiconductor device consists of a P-type MOS (PMOS) transistor and at N-type MOS (NMOS) transistor complementary to the PMOS transistor. The CMOS inverter is able to inverse the phase of input signals by 180°; and has been widely used in logic circuits.
FIG. 1 illustrates a circuit structure of an existing CMOS inverter. As shown in FIG. 1, the CMOS inverter consists of an N-channel enhancement mode MOS (NMOS) transistor 10 and a P-channel enhancement mode MOS (PMOS) transistor 20. The gate (not labeled) of the NMOS transistor 10 and the gate (not labeled) of the PMOS transistor 20 are connected together to be configured as an input port 11 of the CMOS inverter. The drain (not labeled) of the NMOS transistor 10 and the drain (not labeled) of the PMOS transistor 20 are connected together to be configured as an output port 12 of the CMOS inverter. Further, the source (not labeled) of the NMOS transistor 10 is connected with a low potential or grounded; and the source (not labeled) of the PMOS transistor 20 is connected with a high potential Vdd.
FIG. 2 illustrates an existing CMOS inverter. As shown in FIG. 2, the channel enhancement NMOS transistor 10 and the channel enhancement PMOS transistor 20 of the CMOS inverter share a continuous gate 30. Further, a plurality of metal conductive vias 40 are formed on the sources and drains of the NMOS transistor and PMOS transistor to reduce the contact resistance of the sources and the drains.
Because the carrier mobility of electrons in a silicon substrate is greater than the carrier mobility of holes in the silicon substrate, the current density in the NMOS transistor 10 is greater than the current density in the PMOS transistor 20. In order to cause the NMOS transistor 10 and the PMOS transistor 20 to have a same saturation current to have desired performances as a CMOS inverter, the length the channel region of the PMOS transistor 20 is greater than the length of the channel region of the NMOS transistor 10.
However, the delay time of the existing CMOS inverter is relatively long, thus it may affect the performance of the CMOS inverters. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.